• AHDL single-channel serial input convert to 4-lane LVDS data + 1 clock lane video output 
• Supports Pixel Clock fastest at 85MHz. 720P RGB888.
• High-speed video transmission and bi-directional control data over a single Coax or shielded-twisted pair (STP) cable
• CDR on receiver with no external source of reference clock required 
• Robust EMI/EMC tolerance and min. power dissipation
• Multiple EQ capable of long distance transmission
• Single 3.3V power supply, IO supports 1.8V and 3.3V 
• Build In Self Test (BIST) for system diagnostics
• AEC-Q100 Grade 2 qualified
• 48-Pin (7mm*7mm) QFN package
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